In recent years, there have been great advancements in the speed, power, and complexity of integrated circuits, such as application specific integrated circuit (ASIC) chips, random access memory (RAM) chips, microprocessor (μP) chips, and the is like. These advancements have made possible the development of system-on-a-chip (SOC) devices. An SOC device integrates into a single chip many of the components of a complex electronic system, such as a wireless receiver (i.e., cell phone, a television receiver, and the like). SOC devices greatly reduce the size, cost, and power consumption of the system.
System-on-a-chip (SOC) data processors are characterized by a very high degree of integration on a single integrated circuit (IC) chip. Many of the peripheral components now integrated onto the same IC chip as a processor core would have been implemented as separate IC chips in a previous generation of processors. Advantageously, this decreases the amount of board space required, reduces the effects of noise, allows for low-voltage operations, and, in many cases, reduces the pin count of the SOC device.
A data processor core (i.e., central processing unit) generally comprises one or more instruction execution pipelines that execute instructions in sequential steps. Typically an instruction execution pipeline maintains status information for recently executed instructions. The status information is kept in a status register.
If the execution pipeline executes the instructions in sequential order, then the process of maintaining the status information is straightforward. The status information for each instruction is recorded in the status register as each instruction is executed. That is, the contents of the status register are updated after each instruction is executed.
Sometimes, however, instructions are executed out of order. In an out of order execution pipeline, the instructions are not executed sequentially. The order of the instructions may be rearranged. The last instruction to enter the execution pipeline may or may not be the last instruction to leave the execution pipeline. The instructions are issued in order. But after they have been issued, they may go out of order. Therefore, in an out of order execution pipeline a different method must be employed to correctly update the contents of the status register. Sequentially updating the status register as each instruction is executed will cause errors if used in an out of order execution pipeline.
Prior art methods for handing this problem include renaming the status registers to keep track of the out of order instruction executions. An example of a prior art register renaming process is set forth in U.S. Pat. No. 5,826,070. Register renaming methods are generally complex and require significant hardware resources to keep track of the correct order of execution for the instructions in the out of order execution pipeline.
Therefore, there is a need in the art for an apparatus and method that is capable of efficiently updating a status register in an out of order execution pipeline. In particular, there is a need in the art for improved system-on-a-chip (SOC) devices and other large-scale integrated circuits that comprise an apparatus and method that is capable of efficiently updating a status register in an out of order execution pipeline.